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? semiconductor components industries, llc, 2001 january, 2001 rev. 3 1 publication order number: cs5165/d cs5165 5-bit synchronous cpu buck controller the cs5165 synchronous 5bit nfet buck controller is optimized to manage the power of the next generation pentium ii processors. it's v 2 ? control architecture delivers the fastest transient response (100 ns), and best overall voltage regulation in the industry today. it's feature rich design gives end users the maximum flexibility to implement the best price/performance solutions for their end products. the cs5165 has been carefully crafted to maximize performance and protect the processor during operation. it has a 5bit dac on board that holds a 1.0% tolerance over temperature. its on board programmable soft start insures a control start up, and the fet nonoverlap circuitry ensures that both fets do not conduct simultaneously. the on board oscillator can be programmed up to 1.0 mhz to give the designer maximum flexibility in choosing external components and setting systems costs. the cs5165 protects the processor during potentially catastrophic events like overvoltage (ovp) and short circuit. the ovp feature is part of the v 2 architecture and does not require any additional components. during short circuit, the controller pulses the mosfets in a ahiccupo mode (3.0% duty cycle) until the fault is removed. with this method, the mosfets do not overheat or self destruct. the cs5165 is designed for use in both single processor desktop and multiprocessor workstation and server applications. the cs5165's current sharing capability allows the designer to build multiple parallel and redundant power solutions for multiprocessor systems. the cs5165 contains other control and protection features such as power good, enable, and adaptive voltage positioning. it is available in a 16 lead soic wide body package. features ? v 2 control topology ? dual nchannel design ? 100 ns controller transient response ? excess of 1.0 mhz operation ? 5bit dac with 1.0% tolerance ? power good output with internal delay ? enable input provides micropower shutdown mode ? 5.0 v & 12 v operation ? adaptive voltage positioning ? remote sense capability ? current sharing capability ? v cc monitor ? hiccup mode short circuit protection ? overvoltage protection (ovp) ? programmable soft start ? 150 ns pwm blanking ? 65 ns fet nonoverlap time ? 40 ns gate rise and fall times (3.3 nf load) cs5165gdwr16 http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information cs5165gdw16 so16l 46 units/rail so16l 1000 tape & reel pin connections so16l dw suffix case 751g marking diagram 1 cs5165 awlyyww 16 v cc enable 1 16 gate(h) c off pgnd v id4 gate(l) ss pwrgd v id3 lgnd v id2 comp v id1 v fb v id0 1 16
cs5165 http://onsemi.com 2 figure 1. application diagram, 5.0 v to 2.8 v @ 14.2 a for 300 mhz pentium ii comp v ss v fb gate(h) v cc v id0 v id1 v id2 v id3 pgnd ss c off cs5165 pcb trace 6.0 m w 12 v 330 pf 0.1 m f lgnd 1200 m f/10 v 3 1.0 m f pentium ii system v id0 v id1 v id2 v id3 1200 m f/10 v 5 1.2 m h 5.0 v 3.3 k 1000 pf v id4 v id4 irl3103 gate(l) 0.1 m f pwrgd enable irl3103 enable pwrgd v cc absolute maximum ratings* rating value unit operating junction temperature, t j 0 to 150 c lead temperature soldering: reflow: (smd styles only) (note 1.) 230 peak c storage temperature range, t s 65 to +150 c esd susceptibility (human body model) 2.0 kv 1. 60 second maximum above 183 c. *the maximum package power dissipation must be observed.
cs5165 http://onsemi.com 3 absolute maximum ratings pin name pin symbol v max v min i source i sink ic power input v cc 16 v 0.3 v n/a 1.5 a peak, 200 ma dc soft start capacitor ss 6.0 v 0.3 v 200 m a 10 m a compensation capacitor comp 6.0 v 0.3 v 10 ma 1.0 ma voltage feedback input v fb 6.0 v 0.3 v 10 m a 10 m a offtime capacitor c off 6.0 v 0.3 v 1.0 ma 50 ma voltage id dac inputs v id0 v id4 6.0 v 0.3 v 1.0 ma 10 m a highside fet driver gate(h) 16 v 0.3 v 1.5 a peak, 200 ma dc 1.5 a peak, 200 ma dc lowside fet driver gate(l) 16 v 0.3 v 1.5 a peak, 200 ma dc 1.5 a peak, 200 ma dc enable input enable 6.0 v 0.3 v 100 m a 1.0 ma power good output pwrgd 6.0 v 0.3 v 10 m a 30 ma power ground pgnd 0 v 0 v 1.5 a peak, 200 ma dc n/a logic ground lgnd 0 v 0 v 100 ma n/a electrical characteristics (0 c < t a < +70 c; 0 c < t j < +125 c; 8.0 v < v cc < 14 v; 2.8 dac code: (v id4 = v id2 = v id1 = v id0 = 1; v id3 = 0) ; c gate(h) and c gate(l) = 3.3 nf; c off = 330 pf; c ss = 0.1 m f, unless otherwise specified.) characteristic test conditions min typ max unit v cc supply current operating 1.0 v < v fb < v dac (max ontime) no loads on gate(h) and gate(l) 12 20 ma sleep mode enable = 0 v 300 600 m a v cc monitor start threshold gate(h) switching 3.75 3.95 4.15 v stop threshold gate(h) not switching 3.65 3.87 4.05 v hysteresis startstop 80 mv error amplifier v fb bias current v fb = 0 v 0.1 1.0 m a comp source current comp = 1.2 v to 3.6 v; v fb = 2.7 v 15 30 60 m a comp clamp voltage v fb = 2.7 v, adjust comp voltage for comp current = 50 m a 0.85 1.0 1.15 v comp clamp current comp = 0 v 0.4 1.0 1.6 ma comp sink current v comp = 1.2 v; v fb = 3.0 v; v ss > 2.5 v 180 400 800 m a open loop gain note 2. 50 60 db unity gain bandwidth note 2. 0.5 2.0 mhz psrr @ 1.0 khz note 2. 60 85 db gate(h) and gate(l) high voltage at 100 ma measure v cc gate 1.2 2.0 v low voltage at 100 ma measure gate 1.0 1.5 v rise time 1.6 v < gate < (v cc 2.5 v) 40 80 ns fall time (v cc 2.5 v) > gate > 1.6 v 40 80 ns gate(h) to gate(l) delay gate(h) < 2.0 v; gate(l) > 2.0 v 30 65 100 ns gate(l) to gate(h) delay gate(l) < 2.0 v; gate(h) > 2.0 v 30 65 100 ns gate pulldown resistor to pgnd, note 2. 20 50 115 k w 2. guaranteed by design, not 100% tested in production.
cs5165 http://onsemi.com 4 electrical characteristics (continued) (0 c < t a < +70 c; 0 c < t j < +125 c; 8.0 v < v cc < 14 v; 2.8 dac code: (v id4 = v id2 = v id1 = v id0 = 1; v id3 = 0) ; c gate(h) and c gate(l) = 3.3 nf; c off = 330 pf; c ss = 0.1 m f, unless otherwise specified.) characteristic unit max typ min test conditions fault protection ss charge time v fb = 0 v 1.6 3.3 5.0 ms ss pulse period v fb = 0 v 25 100 200 ms ss duty cycle (charge time/period) 100 1.0 3.3 6.0 % ss comp clamp voltage v fb = 2.7 v; v ss = 0 v 0.50 0.95 1.10 v v fb low comparator increase v fb till no ss pulsing and normal offtime 0.9 1.0 1.1 v pwm comparator transient response v fb = 1.2 to 5.0 v. 500 ns after gate(h) (after blanking time) to gate(h) = (v cc 1.0 v) to 1.0 v 100 150 ns minimum pulse width (blanking time) drive v fb. 1.2 to 5.0 v upon gate(h) rising edge (> v cc 1.0 v), measure gate(h) pulse width 50 150 250 ns c off normal offtime v fb = 2.7 v 1.0 1.6 2.3 m s extended offtime v ss = v fb = 0 v 5.0 8.0 12.0 m s timeout timer timeout time v fb = 2.7 v, measure gate(h) pulse width 10 30 50 m s fault duty cycle v fb = 0v 30 50 70 % enable input enable threshold gate(h) switching 0.8 1.15 1.30 v shutdown delay (note 3.) enabletogate(h) < 2.0 v 3.0 m s pullup current enable = 0 v 3.0 7.0 15 m a pullup voltage no load on enable pin 1.30 1.8 3.0 v input resistance enable = 5.0 v, r = (5.0 v v pullup )/i enable 10 20 50 k w power good output low to high delay v fb = (0.8 v dac ) to v dac 30 65 110 m s high to low delay v fb = v dac to (0.8 v dac ) 30 75 120 m s output low voltage v fb = 2.4 v, i pwrgd = 500 m a 0.2 0.3 v sink current limit v fb = 2.4 v, pwrgd = 1.0 v 0.5 4.0 15.0 ma 3. guaranteed by design, not 100% tested in production.
cs5165 http://onsemi.com 5 electrical characteristics (continued) (0 c < t a < +70 c; 0 c < t j < +125 c; 8.0 v < v cc < 14 v; 2.8 dac code: (v id4 = v id2 = v id1 = v id0 = 1; v id3 = 0) ; c gate(h) and c gate(l) = 3.3 nf; c off = 330 pf; c ss = 0.1 m f, unless otherwise specified.) characteristic unit max typ min test conditions voltage identification dac accuracy (all codes except 1 1111) measure v fb = comp (c off = 0 v) 25 c t j 125 c; v cc = 12 v 1.0 +1.0 % v id4 v id3 v id2 v id1 v id0 1 0 0 0 0 3.505 3.540 3.575 v 1 0 0 0 1 3.406 3.440 3.474 v 1 0 0 1 0 3.307 3.340 3.373 v 1 0 0 1 1 3.208 3.240 3.272 v 1 0 1 0 0 3.109 3.140 3.171 v 1 0 1 0 1 3.010 3.040 3.070 v 1 0 1 1 0 2.911 2.940 2.969 v 1 0 1 1 1 2.812 2.840 2.868 v 1 1 0 0 0 2.713 2.740 2.767 v 1 1 0 0 1 2.614 2.640 2.666 v 1 1 0 1 0 2.515 2.540 2.565 v 1 1 0 1 1 2.416 2.440 2.464 v 1 1 1 0 0 2.317 2.340 2.363 v 1 1 1 0 1 2.218 2.240 2.262 v 1 1 1 1 0 2.119 2.140 2.161 v 0 0 0 0 0 2.069 2.090 2.111 v 0 0 0 0 1 2.020 2.040 2.060 v 0 0 0 1 0 1.970 1.990 2.010 v 0 0 0 1 1 1.921 1.940 1.959 v 0 0 1 0 0 1.871 1.890 1.909 v 0 0 1 0 1 1.822 1.840 1.858 v 0 0 1 1 0 1.772 1.790 1.808 v 0 0 1 1 1 1.723 1.740 1.757 v 0 1 0 0 0 1.673 1.690 1.707 v 0 1 0 0 1 1.624 1.640 1.656 v 0 1 0 1 0 1.574 1.590 1.606 v 0 1 0 1 1 1.525 1.540 1.555 v 0 1 1 0 0 1.475 1.490 1.505 v 0 1 1 0 1 1.426 1.440 1.455 v 0 1 1 1 0 1.376 1.390 1.405 v 0 1 1 1 1 1.327 1.340 1.353 v 1 1 1 1 1 1.223 1.247 1.273 v input threshold v id4 , v id3 , v id2 , v id1 , v id0 1.000 1.250 2.400 v input pullup resistance v id4 , v id3 , v id2 , v id1 , v id0 25 50 100 k w input pullup voltage 4.85 5.00 5.15 v
cs5165 http://onsemi.com 6 electrical characteristics (continued) (0 c < t a < +70 c; 0 c < t j < +125 c; 8.0 v < v cc < 14 v; 2.8 dac code: (v id4 = v id2 = v id1 = v id0 = 1; v id3 = 0) ; c gate(h) and c gate(l) = 3.3 nf; c off = 330 pf; c ss = 0.1 m f, unless otherwise specified.) threshold acc racy lower threshold upper threshold threshold accuracy min typ max min typ max unit dac code % of nominal dac output 12 8.5 5.0 5.0 8.5 12 % v id4 v id3 v id2 v id1 v id0 1 0 0 0 0 3.115 3.239 3.363 3.717 3.841 3.965 v 1 0 0 0 1 3.027 3.148 3.268 3.612 3.732 3.853 v 1 0 0 1 0 2.939 3.056 3.173 3.507 3.624 3.741 v 1 0 0 1 1 2.851 2.965 3.078 3.402 3.515 3.629 v 1 0 1 0 0 2.763 2.873 2.983 3.297 3.407 3.517 v 1 0 1 0 1 2.675 2.782 2.888 3.192 3.298 3.405 v 1 0 1 1 0 2.587 2.690 2.793 3.087 3.190 3.293 v 1 0 1 1 1 2.499 2.599 2.698 2.982 3.081 3.181 v 1 1 0 0 0 2.411 2.507 2.603 2.877 2.973 3.069 v 1 1 0 0 1 2.323 2.416 2.508 2.772 2.864 2.957 v 1 1 0 1 0 2.235 2.324 2.413 2.667 2.756 2.845 v 1 1 0 1 1 2.147 2.233 2.318 2.562 2.647 2.733 v 1 1 1 0 0 2.059 2.141 2.223 2.457 2.539 2.621 v 1 1 1 0 1 1.971 2.050 2.128 2.352 2.430 2.509 v 1 1 1 1 0 1.883 1.958 2.033 2.250 2.322 2.397 v 0 0 0 0 0 1.839 1.912 1.986 2.195 2.268 2.341 v 0 0 0 0 1 1.795 1.867 1.938 2.142 2.213 2.285 v 0 0 0 1 0 1.751 1.821 1.810 2.090 2.159 2.229 v 0 0 0 1 1 1.707 1.775 1.843 2.037 2.105 2.173 v 0 0 1 0 0 1.663 1.729 1.796 1.985 2.051 2.117 v 0 0 1 0 1 1.619 1.684 1.748 1.932 1.996 2.061 v 0 0 1 1 0 1.575 1.638 1.701 1.880 1.942 2.005 v 0 0 1 1 1 1.531 1.592 1.653 1.827 1.888 1.949 v 0 1 0 0 0 1.487 1.546 1.606 1.775 1.834 1.893 v 0 1 0 0 1 1.443 1.501 1.558 1.722 1.779 1.837 v 0 1 0 1 0 1.399 1.455 1.511 1.670 1.725 1.781 v 0 1 0 1 1 1.355 1.409 1.463 1.617 1.671 1.724 v 0 1 1 0 0 1.311 1.363 1.416 1.565 1.617 1.669 v 0 1 1 0 1 1.267 1.318 1.368 1.512 1.562 1.613 v 0 1 1 1 0 1.223 1.272 1.321 1.460 1.508 1.557 v 0 1 1 1 1 1.179 1.226 1.273 1.407 1.454 1.501 v 1 1 1 1 1 1.097 1.141 1.185 1.309 1.353 1.397 v
cs5165 http://onsemi.com 7 package pin description package pin # so16l pin symbol function 1, 2, 3, 4, 6 v id0 v id4 voltage id dac input pins. these pins are internally pulled up to 5.0 v if left open. v id4 selects the dac range. when v id4 is high (logic one), the error amp reference range is 2.14 v to 3.45 v with 100 mv increments. when v id4 is low (logic zero), the error amp reference voltage 1.34 v to 2.09 v with 50 mv increments. 5 ss soft start pin. a capacitor from this pin to lgnd sets the soft start and fault timing. 7 c off offtime capacitor pin. a capacitor from this pin to lgnd sets both the normal and extended off time. 8 enable output enable input. this pin is internally pulled up to 1.8 v. a logic low (< 0.8) on this pin disables operation and places the cs5165 into a low current sleep mode. 9 v cc input power supply pin. 10 gate(h) high side switch fet driver pin. 11 pgnd high current ground for the gate(h) and gate(l) pins. 12 gate(l) low side synchronous fet driver pin. 13 pwrgd power good output. open collector output drives low when v fb is out of regulation. ac- tive when enable input is low. 14 lgnd reference ground. all control circuits are referenced to this pin. 15 comp error amp output. pwm comparator reference input. a capacitor to lgnd provides error amp compensation. 16 v fb error amp, pwm comparator, and low v fb comparator feedback input.
cs5165 http://onsemi.com 8 figure 2. block diagram enable ss v id0 v id1 v id2 v id3 v id4 v fb low comparator pwrgd lgnd pwm comparator ss low comparator ss high comparator v cc monitor error amplifier v cc1 v cc c off v gate(h ) v gate(l) pgnd fault fault fault latch pgnd r s q q r s q q r s q latch pwm c off one shot offtime timeout edge triggered extended offtime timeout normal offtime timeout maximum ontime timeout gate(h) = on gate(h) = off 2.0 m a 60 m a 5.0 v 0.7 v 2.5 v 1.0 v 3.95 v 3.87v v fb comp pwm comp + v cc v cc timeout timer (30 m s) enable comparator circuit bias 8.5% +8.5% + + + + + + + + 1.25 v 20 k 7.0 m a 5 bit dac 65 m s delay blanking
cs5165 http://onsemi.com 9 typical performance characteristics 0 2000 4000 6000 8000 10000 12000 14000 16000 0 20 40 60 80 100 120 140 160 180 200 load capacitance (pf) risetime (ns) 0 2000 4000 6000 8000 10000 12000 14000 16000 0 20 40 60 80 100 120 140 160 180 200 load capacitance (pf) falltime (ns) 0 2000 4000 6000 8000 10000 12000 14000 1600 0 0 20 40 60 80 100 120 140 160 180 200 load capacitance (pf) risetime (ns) 0 20 40 60 100 120 0.1 80 0.08 0.06 0.04 0.02 0 0.02 0.04 junction temperature ( c) dac output voltage deviation (%) figure 3. gate(l) risetime vs. load capacitance figure 4. gate(h) risetime vs. load capacitance figure 5. gate(h) & gate(l) falltime vs. load capacitance figure 6. dac output voltage vs. temperature, dac code = 10111, v cc = 12 v v cc = 12 v t a = 25 c v cc = 12 v t a = 25 c 2.14 2.24 2.34 2.44 2.54 2.64 2.74 2.84 2.94 3.04 3.14 3.24 3.34 3.54 3.44 0.25 0.20 0.15 0.10 0.05 0 0.05 1.34 1.39 1.44 1.49 1.54 1.59 1.64 1.69 1.74 1.79 1.84 1.89 1.94 2.04 1.99 0.10 0.08 0.06 0.04 0.02 0 0.04 0.02 2.09 figure 7. percent output error vs. dac voltage setting, v cc = 12 v, t a = 25 c, v id4 = 0 dac output voltage setting (v) figure 8. percent output error vs. dac output voltage setting v cc = 12 v, t a = 25 c, v id4 = 1 dac output voltage setting (v) output error (%) output error (%) v cc = 12 v t a = 25 c
cs5165 http://onsemi.com 10 applications information theory of operation v 2 control method the v 2 method of control uses a ramp signal that is generated by the esr of the output capacitors. this ramp is proportional to the ac current through the main inductor and is offset by the value of the dc output voltage. this control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. this control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. figure 9. v 2 control diagram comp reference voltage + + pwm comparator ramp signal error amplifier error signal output voltage feedback gate(l) e c gate(h) the v 2 control method is illustrated in figure 9. the output voltage is used to generate both the error signal and the ramp signal. since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. the ramp signal also contains the dc portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. a change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the v 2 control scheme to compensate the duty cycle. since the change in inductor current modifies the ramp signal, as in current mode control, the v 2 control scheme has the same advantages in line transient response. a change in load current will have an affect on the output voltage, altering the ramp signal. a load step immediately changes the state of the comparator output, which controls the main switch. load transient response is determined only by the comparator response time and the transition speed of the main switch. the reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. the error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. the main purpose of this `slow' feedback loop is to provide dc accuracy. noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. line and load regulation are drastically improved because there are two independent voltage loops. a voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. this change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. a current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. the v 2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. constant off time to maximize transient response, the cs5165 uses a constant off time method to control the rate of output pulses. during normal operation, the off time of the high side switch is terminated after a fixed period, set by the c off capacitor. to maintain regulation, the v 2 control loop varies switch on time. the pwm comparator monitors the output voltage ramp, and terminates the switch on time. constant off time provides a number of advantages. switch duty cycle can be adjusted from 0 to 100% on a pulse by pulse basis when responding to transient conditions. both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. pwm slope compensation to avoid subharmonic oscillations at high duty cycles is avoided. switch on time is limited by an internal 30 m s (typical) timer, minimizing stress to the power components. programmable output the cs5165 is designed to provide two methods for programming the output voltage of the power supply. a five bit on board digital to analog converter (dac) is used to program the output voltage within two different ranges. the first range is 2.14 v to 3.54 v in 100 mv steps, the second is 1.34 v to 2.09 v in 50 mv steps, depending on the digital input code. if all five bits are left open, the cs5165 enters adjust mode. in adjust mode, the designer can choose any output voltage by using resistor divider feedback to the v fb pin, as in traditional controllers. the cs5165 is specifically designed to meet or exceed intel's pentium ii specifications.
cs5165 http://onsemi.com 11 start up until the voltage on the v cc supply pin exceeds the 3.95 v monitor threshold, the soft start and gate pins are held low. the fault latch is reset (no fault condition). the output of the error amplifier (comp) is pulled up to 1.0 v by the comparator clamp. when the v cc pin exceeds the monitor threshold, the ga te(h) output is activated, and the soft start capacitor begins charging. the gate(h) output will remain on, enabling the nfet switch, until terminated by either the pwm comparator, or the maximum on time timer. if the maximum on time is exceeded before the regulator output voltage achieves the 1.0 v level, the pulse is terminated. the gate(h) pin drives low, and the ga te(l) pin drives high for the duration of the extended off time. this time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. the gate(l) pin will then drive low, the gate(h) pin will drive high, and the cycle repeats. when regulator output voltage achieves the 1.0 v level present at the comp pin, regulation has been achieved and normal off time will ensue. the pwm comparator terminates the switch on time, with off time set by the c off capacitor. the v 2 control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. the soft start and comp capacitors will charge to their final levels, providing a controlled turn on of the regulator output. regulator turn on time is determined by the comp capacitor charging to its final value. its voltage is limited by the soft start comp clamp and the voltage on the soft start pin. power supply sequencing the cs5165 offers inherent protection from undefined start up conditions, regardless of the 12 v and 5.0 v supply power up sequencing. the turn on slew rates of the 12 v and 5.0 v power supplies can be varied over wide ranges without affecting the output voltage or causing detrimental effects to the buck regulator. figure 10. demonstration board startup in response to increasing 12 v and 5.0 v input voltages. extended off time is followed by normal off time operation when output voltage achieves regulation to the error amplifier output. m 250 m s trace 3 12 v input (v cc ) (5.0 v/div.) trace 1 regulator output voltage (1.0 v/div.) trace 4 5.0 v input (1.0 v/div.) trace 2 inductor switching node (2.0 v/div.) figure 11. demonstration board startup waveforms trace 2 comp pin (error amplifier output) (1.0 v/div.) trace 1 soft start pin (2.0 v/div.) trace 4 regulator output voltage (1.0 v/div.)
cs5165 http://onsemi.com 12 figure 12. demonstration board enable startup waveforms m 10.0 m s trace 1 regulator output voltage (1.0 v/div.) trace 2 inductor switching node (5.0 v/div.) normal operation during normal operation, switch off time is constant and set by the c off capacitor. switch on time is adjusted by the v 2 control loop to maintain regulation. this results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. output voltage ripple will be determined by inductor ripple current working and the esr of the output capacitors (see figures 13 and 14). figure 13. normal operation showing output inductor ripple current and output voltage ripple, 0.5 a load, v out = +2.84 v (dac = 10111) trace 1 gate(h) (10 v/div.) trace 2 inductor switching node (5.0 v/div.) trace 3 output inductor ripple current (2.0 a/div.) trace 4 v out ripple (20 mv/div.) trace 1 gate(h) (10 v/div.) trace 2 inductor switching node (5.0 v/div.) trace 3 output inductor ripple current (2.0 a/div.) trace 4 v out ripple (20 mv/div.) figure 14. normal operation showing output inductor ripple current and output voltage ripple, i load = 14 a, v out = +2.84 v (dac = 10111) transient response the cs5165 v 2 control loop's 100 ns reaction time provides unprecedented transient response to changes in input voltage or output current. pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. overall load transient response is further improved through a feature called aadaptive voltage positioningo. this technique prepositions the output capacitors voltage to reduce total output voltage excursions during changes in load. holding tolerance to 1.0% allows the error amplifiers reference voltage to be targeted +40 mv high without compromising dc accuracy. a adroop resistoro, implemented through a pc board trace, connects the error amps feedback pin (v fb ) to the output capacitors and load and carries the output current. with no load, there is no dc drop across this resistor, producing an output voltage tracking the error amps, including the +40 mv offset. when the full load current is delivered, an 80 mv drop is developed across this resistor. this results in output voltage being offset 40 mv low. the result of adaptive voltage positioning is that additional margin is provided for a load transient before reaching the output voltage specification limits. when load
cs5165 http://onsemi.com 13 current suddenly increases from its minimum level, the output capacitor is prepositioned +40 mv. conversely, when load current suddenly decreases from its maximum level, the output capacitor is prepositioned 40 mv (see figures 15, 16, and 17). for best transient response, a combination of a number of high frequency and bulk output capacitors are usually used. if the maximum ontime is exceeded while responding to a sudden increase in load current, a normal offtime occurs to prevent saturation of the output inductor. figure 15. output voltage transient response to a 14 a load pulse, v out = +2.84 v (dac = 10111) trace 4 v out (100 mv/div.) trace 3 load current (5.0 a/10 mv/div.) figure 16. output voltage transient response to a 14 a load step, v out = +2.84 v (dac = 10111) trace 1 gate(h) (10 v/div.) trace 2 inductor switching node (5.0 v/div.) trace 3 load current (5.0 a/div) trace 4 v out (100 mv/div.) figure 17. output voltage transient response to a 14 a load turnoff, v out = +2.84 v (dac = 10111) trace 1 gate(h) (10 v/div.) trace 2 inductor switching node (5.0 v/div.) trace 3 load current (5.0 a/div) trace 4 v out (100 mv/div.) protection and monitoring features short circuit protection a lossless hiccup mode short circuit protection feature is provided, requiring only the soft start capacitor to implement. if a short circuit c ondition occurs the v fb low comparator sets the fault latch. this causes the top fet to shut off, disconnecting the regulator from it's input voltage. the soft start capacitor is then slowly discharged by a 2.0 m a current source until it reaches it's lower 0.7 v threshold. the regulator will then attempt to restart normally, operating in it's extended off time mode with a 50% duty cycle, while the soft start capacitor is charged with a 60 m a charge current. if the short circuit condition persists, the regulator output will not achieve the 1.0 v low v fb comparator threshold before the soft start capacitor is charged to it's upper 2.5 v threshold. if this happens the cycle will repeat itself until the short is removed. the soft start charge/discharge current ratio sets the duty cycle for the pulses (2.0 m a/60 m a = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%). this protection feature results in less stress to the regulator components, input power supply, and pc board traces than occurs with constant current limit protection (see figures 18 and 19). if the short circuit condition is removed, output voltage will rise above the 1.0 v level, preventing the fault latch from being set, allowing normal operation to resume.
cs5165 http://onsemi.com 14 figure 18. demonstration board h iccup mode short circuit protection. gate pulses are delivered while the soft start capacitor charges, and cease during discharge m 25.0 ms trace 3 soft start timing capacitor (1.0 v/div.) trace 4 5.0 v supply voltage (2.0 v/div.) trace 2 inductor switching node (2.0 v/div.) figure 19. demonstration board startup with regulator output shorted to ground m 50.0 m s trace 4 5.0 v from pc power supply (2.0 v/div.) trace 2 inductor switching node (2.0 v/div.) overvoltage protection overvoltage protection (ovp) is provided as result of the normal operation of the v 2 control topology and requires no additional external components. the control loop responds to an overvoltage condition within 100 ns, causing the top mosfet to shut off, disconnecting the regulator from it's input voltage. the bottom mosfet is then activated, resulting in a acrowbaro action to clamp the output voltage and prevent damage to the load (see figures 20 and 21 ). the regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. the bottom fet and board trace must be properly designed to implement the ovp function. if a dedicated ovp output is required, it can be implemented using the circuit in figure 22. in this figure the ovp signal will go high (overvoltage condition), if the output voltage (v core ) exceeds 20% of the voltage set by the particular dac code and provided that pwrgd is low. it is also required that the overvoltage condition be present for at least the pwrgd delay time for the ovp signal to be activated. the resistor values shown in figure 22 are for v dac = +2.8 v (dac = 10111). the v ovp (overvoltage trippoint) can be set using the following equation: v ovp v beq3 1 r2 r1 figure 20. ovp response to an inputtooutput short circuit by immediately providing 0% duty cycle, crowbarring the input voltage to ground m 10.0 m s trace 1 regulator output voltage (1.0 v/div.) trace 2 inductor switching node 5.0 v/div.) trace 4 5.0 v from pc power supply (5.0 v/div.) figure 21. ovp response to an inputtooutput short circuit by pulling the input voltage to ground m 5.00 ms trace 1 regulator output voltage (1.0 v/div.) trace 4 5.0 v from pc power supply (2.0 v/div.)
cs5165 http://onsemi.com 15 figure 22. circuit to implement a dedicated ovp output using the cs5165 cs5165 pwrgd +5.0 v 10 k q1 2n3906 2n3904 q2 20 k 5.0 k +5.0 v 10 k 10 k ovp q3 2n3906 56 k 15 k v core r1 r2 output enable circuit the enable pin (pin 8) is used to enable or disable the regulator output voltage, and is consistent with ttl dc specifications. it is internally pulledup. if pulled low (below 0.8 v), the output voltage is disabled. at the same time the power good and soft start pins are pulled low, so that when normal operation resumes powerup of the cs5165 goes through the soft start sequence. upon pulling the enable pin low, the internal ic bias is completely shut off, resulting in total shutdown of the controller ic. power good circuit the power good pin (pin 13) is an opencollector signal consistent with ttl dc specifications. it is externally pulledup, and is pulled low (below 0.3 v) when the regulator output voltage typically exceeds 8.5% of the nominal output voltage. maximum output voltage deviation before power good is pulled low is 12%. figure 23. pwrgd signal becomes logic high as v out enters 8.5% of lower pwrgd threshold, v out = +2.84 v (dac = 10111) trace 4 v out (1.0 v/div.) trace 2 pwrgd (2.0 v/div.) figure 24. power good response to an out of regulation condition trace 4 v fb (1.0 v/div.) trace 2 pwrgd (2.0 v/div.) figure 24 shows the relationship between the regulated output voltage v fb and the power good signal. to prevent power good from interrupting the cpu unnecessarily, the cs5165 has a builtin delay to prevent noise at the v fb pin from toggling power good. the internal time delay is designed to take about 75 m s for power good to go low and 65 m s for it to recover. this allows the power good signal to be completely insensitive to out of regulation conditions that are present for a duration less than the built in delay (see figure 25). it is therefore required that the output voltage attains an out of regulation or in regulation level for at least the builtin delay time duration before the power good signal can change state. figure 25. power good is insensitive to out of regulation conditions that are present for a duration less than the built in delay trace 4 v fb (1.0 v/div.) trace 2 pwrgd (2.0 v/div.)
cs5165 http://onsemi.com 16 selecting external components the cs5165 buck regulator can be used with a wide range of external power components to optimize the cost and performance of a particular design. the following information can be used as general guidelines to assist in their selection. nfet power transistors both logic level and standard fets can be used. the reference designs derive gate drive from the 12 v supply which is generally available in most computer systems and utilize logic level fets. a charge pump may be easily implemented to support 5.0 v only systems. multiple fet's may be paralleled to reduce losses and improve efficiency and thermal management. voltage applied to the fet gates depends on the application circuit used. both upper and lower gate driver outputs are specified to drive to within 1.5 v of ground when in the low state and to within 2.0 v of their respective bias supplies when in the high state. in practice, the fet gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller ic. for the typical application where v cc = 12 v and 5.0 v is used as the source for the regulator output current, the following gate drive is provided: v gs(bottom) 12 v v gs(top) 12 v 5.0 v 7.0 v (see figure 26) figure 26. gate drive waveforms depicting rail to rail swing trace 3 gate(h) (10 v/div.) trace 1 gate(h) 5.0 v in trace 4 gate(l) (10 v/div.) trace 2 inductor switching node (5.0 v/div.) figure 27. normal operation showing the guaranteed nonoverlap time between the high and lowside mosfet gate drives, i load = 14 a trace 1 = gate(h) (5.0 v/div.) trace 2 = gate(l) (5.0 v/div.) @ 2.2 v the cs5165 provides adaptive control of the external nfet conduction times by guaranteeing a typical 65 ns nonoverlap between the upper and lower mosfet gate drive pulses. this feature eliminates the potentially catastrophic effect of ashootthrough currento, a condition during which both fets conduct causing them to overheat, selfdestruct, and possibly inflict irreversible damage to the processor. the most important aspect of fet performance is rds on , which effects regulator efficiency and fet thermal management requirements. the power dissipated by the mosfets may be estimated as follows: switching mosfet: power i load 2 rds on duty cycle synchronous mosfet: power i load 2 rds on ( 1 duty cycle ) duty cycle = v out (i load rds on of synch fet ) v in (i load rds on of synch fet ) (i load rds on of switch fet ) off time capacitor (c off ) the c off timing capacitor sets the regulator off time: t off c off 4848.5
cs5165 http://onsemi.com 17 the preceding equations for duty cycle can also be used to calculate the regulator switching frequency and select the c off timing capacitor: c off perioid ( 1 duty cycle ) 4848.5 where: period 1 switching frequency schottky diode for synchronous fet for synchronous operation, a schottky diode may be placed in parallel with the synchronous fet to conduct the inductor current upon turn off of the switching fet to improve efficiency. the cs5165 reference circuit does not use this device due to it's excellent design. instead, the body diode of the synchronous fet is utilized to reduce cost and conducts the inductor current. for a design operating at 200 khz or so, the low nonoverlap time combined with schottky forward recovery time may make the benefits of this device not worth the additional expense. the power dissipation in the synchronous mosfet due to body diode conduction can be estimated by the following equation: p ower v bd i load conduction time switching frequenc y where v bd = the forward drop of the mosfet body diode. for the cs5165 demonstration board: power 1.6 v 14.2 a 100 ns 200 khz 0.45 w this is only 1.1% of the 40 w being delivered to the load. adroopo resistor for adaptive voltage positioning adaptive voltage positioning is used to help keep the output voltage within specification during load transients. to implement adaptive voltage positioning a adroop resistoro must be connected between the output inductor and output capacitors and load. this resistor carries the full load current and should be chosen so that both dc and ac tolerance limits are met. an embedded pc trace resistor has the distinct advantage of near zero cost implementation. however, this droop resistor can vary due to three reasons: 1) the sheet resistivity variation causes the thickness of the pcb layer to vary. 2) the mismatch of l/w, and 3) temperature variation. 1. sheet resistivity for one ounce copper, the thickness variation typically 1.15 mil to 1.35 mil. therefore the error due to sheet resistivity is: 1.35 1.15 1.25 16% 2. mismatch due to l/w. the variation in l/w is governed by variations due to the pcb manufacturing process that affect the geometry and the power dissipation capability of the droop resistor. the error due to l/w mismatch is typically 1.0%. 3. thermal considerations. due to i 2 r power losses the surface temperature of the droop resistor will increase causing the resistance to increase. also, the ambient temperature variation will contribute to the increase of the resistance, according to the formula: r r 20 [1 20 (t 20)] where: r 20 = resistance at 20 c 0.00393 c t = operating temperature r = desired droop resistor value for temperature t = 50 c, the % r change = 12% droop resistor tolerance tolerance due to sheet resistivity variation 16% tolerance due to l/w error 1.0% tolerance due to temperature variation 12% total tolerance for droop resistor 29% in order to determine the droop resistor value the nominal voltage drop across it at full load has to be calculated. this voltage drop has to be such that the output voltage full load is above the minimum dc tolerance spec. v droop(typ) [v dac(min) v dc(min) ] 1 r droop(tolerance ) example: for a 300 mhz pentium ii, the dc accuracy spec is 2.74 < v cc(core) < 2.9 v, and the ac accuracy spec is 2.67 v < v cc(core) < 2.9 3v. the cs5165 dac output voltage is +2.812 v < v dac < +2.868 v. in order not to exceed the dc accuracy spec, the voltage drop developed across the resistor must be calculated as follows: v droop(typ) [v dac(min) v dc pentiumii(min)] 1 r droop(tolerance ) 2.812 v 2.74 v 1.3 56 mv with the cs5165 dac accuracy being 1.0%, the internal error amplifier's reference voltage is trimmed so that the output voltage will be 40 mv high at no load. with no load, there is no dc drop across the resistor, producing an output voltage tracking the error amplifier output voltage, including the offset. when the full load current is delivered, a drop of 56 mv is developed across the resistor. therefore, the regulator output is prepositioned at 40 mv above the nominal output voltage before a load turnon. the total voltage drop due to a load step is d v40 mv and the deviation from the nominal output voltage is 40 mv smaller than it would be if there was no droop resistor. similarly at full load the regulator output is prepositioned at 16 mv below the nominal voltage before a load turnoff. the total voltage increase due to a load turnoff is d v16 mv and the deviation from the nominal output voltage is 16 mv smaller than it would be if there was no droop resistor. this is because the output capacitors are precharged to value that is either 40 mv above the nominal output voltage before a
cs5165 http://onsemi.com 18 load turnon or, 16 mv below the nominal output voltage before a load turnoff (see figure 15). obviously, the larger the voltage drop across the droop resistor ( the larger the resistance), the worse the dc and load regulation, but the better the ac transient response. design rules for using a droop resistor the basic equation for laying an embedded resistor is: r ar l a or r l (w t) where: a = w t = crosssectional area r = the copper resistivity ( mw mil) l = length (mils) w = width (mils) t = thickness (mils) for most pcbs the copper thickness, t, is 35 m m (1.37 mils) for one ounce copper. r = 717.86 mw mil for a pentium ii load of 14.2 a the resistance needed to create a 56 mv drop at full load is: response droop 56 mv i out 56 mv 14.2 a 3.9 m the resistivity of the copper will drift with the temperature according to the following guidelines: r 12%@t a 50 c r 34%@t a 100 c droop resistor width calculations the droop resistor must have the ability to handle the load current and therefore requires a minimum width which is calculated as follows (assume one ounce copper thickness): w i load 0.05 where: w = minimum width (in mils) required for proper power dissipation, and i load load current amps. the pentium ? ii maximum load current is 14.2 a. therefore: w 14.2 a 0.05 284 mils 0.7213 cm droop resistor length calculation l r droop w t 0.0039 284 1.37 717.86 2113 mil 5.36 cm output inductor the inductor should be selected based on its inductance, current capability, and dc resistance. increasing the inductor value will decrease output voltage ripple, but degrade transient response. inductor ripple current ripple current [(v in v out ) v out ] (switching frequency l v in ) example: v in = +5.0 v, v out = +2.8 v, i load = 14.2 a, l = 1.2 m h, freq = 200 khz ripple current [(5.0 v 2.8 v) 2.8 v] [200 khz 1.2 h 5.0 v] 5.1 a output ripple voltage v ripple inductor ripple current output capacitor esr example: v in = +5.0 v, v out = +2.8 v, i load = 14.2 a, l = 1.2 m h, switching frequency = 200 khz output ripple voltage = 5.1 a output capacitor esr (from manufacturer's specs) esr of output capacitors to limit output voltage spikes esr v out i out this applies for current spikes that are faster than regulator response time. printed circuit board resistance will add to the esr of the output capacitors. in order to limit spikes to 100 mv for a 14.2 a load step, esr = 0.1/14.2 = 0.007 w inductor peak current peak current maximum load current ripple current 2 example: v in = +5.0 v, v out = +2.8 v, i load = 14.2 a, l = 1.2 m h, freq = 200 khz peak current 14.2 a (5.1 2) 16.75 a a key consideration is that the inductor must be able to deliver the peak current at the switching frequency without saturating. response time to load increase (limited by inductor value unless maximum ontime is exceeded) response time l i out (v in v out ) example: v in = +5.0 v, v out = +2.8 v, l = 1.2 m h, 14.2 a change in load current response time 1.2 h 14.2 a (5.0 v 2.8 v) 7.7 s response time to load decrease (limited by inductor value) response time l change in i out v out
cs5165 http://onsemi.com 19 example: v out = +2.8 v, 14.2 a change in load current, l = 1.2 m h response time 1.2 h 14.2 a 2.8 v 6.1 s input and output capacitors these components must be selected and placed carefully to yield optimal results. capacitors should be chosen to provide acceptable ripple on the input supply lines and regulator output voltage. key specifications for input capacitors are their ripple rating, while esr is important for output capacitors. for best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. thermal management thermal considerations for power mosfets and diodes in order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a maximum of 150 c or lower. the thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows: thermal impedance t junction(max) t ambient power a heatsink may be added to to220 components to reduce their thermal impedance. a number of pc board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. emi management as a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. when designing for compliance with emi/emc regulations, additional components may be added to reduce noise emissions. these components are not required for regulator operation and experimental results may allow them to be eliminated. the input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. placement of the power component to minimize routing distance will also help to reduce emissions. layout guidelines when laying out the cpu buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the cs5165. 1. rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2. keep high currents out of logic grounds. 3. avoid ground loops as they pick up noise. use star or single point grounding. the source of the lower (synchronous fet) is an ideal point where the input and output gnd planes can be connected. 4. for doublesided pcbs a single large ground plane is not recommended, since there is little control of where currents flow and the large surface area can act as an antenna. 5. even though double sided pcbs are usually suf ficient for a good layout, fourlayer pcbs are the optimum approach to reducing susceptibility to noise. use the two internal layers as the +5.0 v and gnd planes, and the top and bottom layers for the vias. 6. keep the inductor switching node small by placing the output inductor, switching and synchronous fets close together. 7. the fet gate traces to the ic must be as short, straight, and wide as possible. ideally, the ic has to be placed right next to the fets. 8. use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. 9. place the switching fet as close to the +5.0 v input capacitors as possible. 10. place the output capacitors as close to the load as possible. 11. place the v fb filter resistor in series with thev fb pin (pin 16) right at the pin. 12. place the v fb filter capacitor right at the v fb pin (pin 16). 13. the adroopo resistor (embedded pcb trace) has to be wide enough to carry the full load current. 14. place the v cc bypass capacitor as close as possible to the v cc pin.
cs5165 http://onsemi.com 20 + comp enable v fb v gate(h) v gate(l) pwrgd v cc v id0 v id1 v id2 v id3 v id4 pgnd ss c off cs5165 6.0 m w 330 pf lgnd 1200 m f/10 v 3 1.2 m h si4410dy 1.0 m f 3.3 k 0.1 m f 1000 pf 5.0 v mbrs120 1200 m f/10 v 5 figure 28. additional application diagram, +5.0 v to +2.8 v @ 14.2 a for 300 mhz pentium ii pentium ii system droop resistor (embedded pcb trace) 0.1 m f si9410dy mbrs120 mbrs120 1.0 m f enable pwrgd v id0 v id1 v id2 v id3 v id4 v cc v ss
cs5165 http://onsemi.com 21 package dimensions so16l dw suffix case 751g03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 package thermal data parameter so16l unit r q jc typical 23 c/w r q ja typical 105 c/w
cs5165 http://onsemi.com 22 notes
cs5165 http://onsemi.com 23 notes
cs5165 http://onsemi.com 24 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs5165/d v 2 is a trademark of switch power, inc. pentium is a registered trademark of intel corporation. north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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